The Design And Verification Conference & Exhibition India 2025 (DVCon India 2025) is the tenth edition of India’s leading forum for practical tools, languages, standards, and methods in electronic-system and integrated-circuit design and verification. The event will be held on September 10–11, 2025 in Bangalore. Under the theme “Architecture to Analytics – A2A”, DVCon India 2025 maps the full design lifecycle: from high-level architecture and modeling to data-driven analytics used in verification and validation. The conference brings together engineers, researchers, educators, tool vendors, and standards bodies to focus on real work practices and real problems.

This edition keeps established focus groups—System & IP Modeling, Architecture & Design, RISC-V, Analog & Mixed-Signal Verification, and Post-Silicon Validation—and layers them with analytics and measurement practices that are increasingly central to complex SoC delivery. Attendees will find tutorials, technical talks, panels, hands-on workshops, poster sessions, and an exhibition floor where vendors demo tools, verification flows, and IP. The program prioritizes practical, transferable outcomes: code examples, test plans, verification strategies, and post-silicon debug recipes that engineers can adopt immediately.

DVCon India 2025 aims to both teach and provoke. It asks how architectural choices shape verification cost. It asks how analytics can close the loop between pre-silicon assumptions and silicon reality. It also celebrates a decade of DVCon India and invites nominations for awards that honor institutions and individuals making measurable contributions to education, verification practice, diversity, and lifetime achievement. If you work on design, verification, or test, this event is a concentrated way to learn, meet vendors, and influence the direction of tools and standards in India and beyond.

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Program and Focus Areas

Theme and Scope

Design And Verification Conference & Exhibition India 2025 centers on Architecture to Analytics (A2A). The theme recognizes that modern semiconductor projects require tight feedback loops. Architecture choices determine verification scope. Analytics and data science transform verification from art to repeatable engineering. Sessions will show concrete examples where analytics found escapes, accelerated sign-off, or guided silicon bring-up.

Technical Tracks and Formats

The conference includes a mix of formats:

• Keynotes and plenaries by industry leaders.

• Focus group sessions on System & IP Modeling, Architecture & Design, RISC-V, Analog & Mixed-Signal Verification, and Post-Silicon Validation.

• Hands-on tutorials and tool workshops.

• Poster sessions and short papers emphasizing practical lessons.

• Vendor demos and an exhibition floor for toolchains, IP, and test solutions.

Who Should Attend

• Design engineers and verification engineers.

• SoC architects and IP leads.

• Test and post-silicon validation teams.

• R&D managers and technical leads.

• Academics and VLSI educators.

• Tool vendors, integrators, and standards contributors.

Practical Outcomes to Expect

DVCon India 2025 focuses on usable outcomes:

• Reference verification plans and checklists.

• Examples of SystemC/TLM, UVM, and RISC-V verification flows.

• Data-driven dashboards and anomaly detection recipes for silicon bring-up.

• Post-silicon strategies for debug and coverage closure.

Exhibition and Industry Presence

Vendors will demonstrate EDA tools, verification IP, emulation and FPGA prototyping platforms, measurement instruments, and analytics platforms. The exhibition supports short demos and one-to-one meetings with tool experts.

Awards & Recognition

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Exhibition, Workshops and Practical Labs

Tutorials and Workshops

Workshops at DVCon India focus on tool-driven learning. Expect full-day tutorials on UVM testbench patterns, portable stimulus methods, SystemC/TLM modeling, RISC-V verification flows, and mixed-signal verification strategies. Labs will let attendees run emulation jobs, inspect waveforms, and build small measurement pipelines that push verification telemetry into analytics tools.

System & IP Modeling Track

Modern SoC schedules demand early system modeling. This track covers behavior modeling, power/perf tradeoffs, virtual platform validation, and IP integration. Speakers show how early SystemC and transaction-level models reduce risks and create test harnesses for software and verification.

Architecture & Design Track

Architects present lessons on partitioning, interface contracts, and observability design. Sessions examine how micro-architecture decisions influence verification strategies. Case studies reveal how modest changes in observability points or telemetry hooks save weeks in debug.

RISC-V Focus

RISC-V continues to grow as an open ISA of choice. The RISC-V focus group highlights verification methodologies for cores, subsystems, and compliance suites. Topics include ISA verification, formal checking, coverage metrics, and co-verification with software stacks.

Analog & Mixed-Signal Verification

Mixed-signal verification remains a bottleneck. This track brings analog modeling practices, cadence between analog and digital teams, and post-silicon calibration strategies. Practical demos show how data from silicon tests feeds back into analog model refinement.

Post-Silicon Validation

Post-silicon sessions cover bring-up, failure analysis, debug instrumentation, and long-term telemetry. Engineers share strategies for building reproducible silicon debug flows and using analytics to find rare corner failures.

Posters and Short Papers

Poster sessions prioritize real problems and quick wins. The format favors “we tried this, here’s the script, here are the results.” These concise contributions often spark immediate collaboration between tool vendors and engineering teams.

Networking and Collaboration

DVCon India 2025 places strong emphasis on networking. Expect curated meetups, vendor-user clinics, and focus-group roundtables. These interactions often lead to direct tool trials, pilot projects, and academic-industry partnerships.

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Architectural Analysis

Although DVCon India 2025 is a conference rather than a building, an architectural analysis is useful if we view the event as a designed system:

Design logic. The conference is organized as layered systems. At the top are high-level themes (Architecture to Analytics). Beneath those are tracks (modeling, verification, RISC-V, analog, post-silicon). Below them are concrete workflows: tutorials, labs, and demos. This layered design mirrors good system architecture: clear separation of concerns, modular components, and defined interfaces between tracks.

Material use. In conference terms, “materials” are languages, tools, and standards—SystemC, UVM, Python for analytics, formal engines, emulators, and RISC-V test suites. DVCon’s material palette emphasizes open standards and interoperable toolchains. The exhibition space uses demonstration rigs (emulators, FPGA prototyping boards), telemetry dashboards, and reproducible scripts as the tangible artefacts that communicate intent.

Context. Bangalore is a natural host: a dense ecosystem of chip design firms, startups, universities, and R&D centers. DVCon India 2025 sits in a context of growing local silicon activity, IP development, and increasing adoption of RISC-V and open tools in the region.

Critical interpretation. The conference’s strength lies in linking architecture decisions to measurable verification outcomes. However, there are tensions. Practical workshops are always in demand, but time is limited. Vendors may push product messages during technical sessions. Another risk is fragmentation: with many focus groups running, attendees may struggle to compose a coherent learning path. The remedy lies in curated learning tracks and clear lab prerequisites.

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Project Importance

What it teaches architects and designers. DVCon India 2025 teaches that architecture is verification aware. Architects must design with observability, testability, and telemetry in mind. The conference shows how early modeling reduces downstream verification cost and how analytics accelerate closure.

Contribution to architectural thinking and typology. The event reframes chip design typologies by embedding verification and analytics into the architectural phase. It promotes a typology where blocks are designed not only for performance and power, but also for debuggability and data-driven validation. This shift has implications for IP contracts, interface standards, and integration practices.

Why it matters now. System complexity is rising while schedules compress. Analytics and automation reduce human guesswork. The conference matters because it moves the industry from anecdote to reproducible practice. It helps close the gap between academic methods and production reality. For India specifically, DVCon India gathers the ecosystem needed to grow local capability in VLSI and verification and to build industrial strength in SoC delivery.

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✦ ArchUp Editorial Insight

DVCon India 2025 concisely connects system architecture with verification analytics. The program’s layered layout—tutorials, tracks, labs, and demos—creates a practical learning path. Visual identity is functional: clear slides, live dashboards, and demonstrator rigs dominate the halls. Yet the event risks fragmentation: too many parallel sessions can scatter attention and dilute learning depth. Could a stronger curated pathway reduce cognitive load and increase applied outcomes? Still, DVCon’s core value remains its focus on transferable practice—real scripts, repeatable flows, and measurable verification wins.

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Conclusion

The Design And Verification Conference & Exhibition India 2025 is a timely, practical, and tightly focused industry event. It celebrates ten years of DVCon India while pushing the agenda from architecture design decisions to analytics-driven verification. For engineers, it offers hands-on learning and real examples that can be applied the week after the conference. For managers and architects, it demonstrates how architectural choices directly influence verification schedule, risk, and cost.

DVCon India 2025 also plays a strategic role for the Indian semiconductor ecosystem. By gathering tool vendors, IP providers, universities, and engineering teams, it accelerates capability building and cross-sector collaboration. Awards recognize institutions and individuals who move the industry forward, and the exhibition gives newcomers a clear line of sight to tools and partners they need.

If you design, verify, or validate silicon, this conference is a concentrated investment of time with immediate return. You gain techniques, scripts, and human contacts that shorten debug cycles and improve sign-off confidence. As systems get more complex and analytics become indispensable, DVCon India 2025 stands out as the practical forum where architecture meets analytics—and where engineers leave with tools they can use on real projects.

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